2.5v or 3.3v, 200-mhz, 9-output clock drive r cy29350 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07474 rev. *a revised july 26, 2004 features ? output frequency range: 25 mhz to 200 mhz ? input frequency range: 6.25 mhz to 31.25 mhz ? 2.5v or 3.3v operation ? split 2.5v/3.3v outputs ? 2.5% max output duty cycle variation ? nine clock outputs: drive up to 18 clock lines ? two reference clock inputs: xtal or lvcmos ? 150-ps max output-output skew ? phase-locked loop (pll) bypass mode ? spread aware? ? output enable/disable ? pin-compatible with mpc9350 ? industrial temperature range: ?40c to +85c ? 32-pin 1.0mm tqfp package functional description the cy29350 is a low-voltage high-performance 200-mhz pll-based clock driver designed for high speed clock distri- bution applications. the cy29350 features xtal and lvcmos reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. bank a divi des the vco output by 2 or 4 while the other banks divide by 4 or 8 per sel(a:d) settings, see . these dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. each lvcmos co mpatible output can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. the pll is ensured stable given that the vco is configured to run between 200 mhz to 500 mhz. this allows a wide range of output frequencies from 25 mhz to 200 mhz. the internal vco is running at multiples of the input reference clock set by the feedback divider, see table 1. when pll_en is low, pll is bypassed and the reference clock directly feeds the output dividers. this mode is fully static and the minimum input clock frequency specification does not apply. block diagram pin configuration osc phase detector vco 200 - 500mhz lpf 16 / 32 2 / 4 4 / 8 4 / 8 4 / 8 qa qb qc0 qc1 qd0 qd1 qd2 qd3 qd4 sela pll_en tclk ref_sel xin xout fb_sel selb selc oe# seld cy29350 ref_sel pll_en tclk vss qa vddqb qb vss xin oe# vdd qd4 vss qd3 vddqd qd2 qc0 vddqc qc1 vss qd0 vddqd qd1 vss avdd fb_sel sela selb selc seld avss xout 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 [+] feedback
cy29350 document #: 38-07474 rev. *a page 2 of 7 pin definitions [1] pin name i/o type description 8xoutoanalog oscillator output . connect to a crystal. 9xinianalog oscillator input . connect to a crystal. 30 tclk i, pd lvcmos lvcmos/lvttl reference clock input 28 qa o lvcmos clock output bank a 26 qb o lvcmos clock output bank b 22, 24 qc(1:0) o lvcmos clock output bank c 12, 14, 16, 18, 20 qd(4:0) o lvcmos clock output bank d 2 fb_sel i, pd lvcmos internal feedback select input . see table 1 . 10 oe# i, pd lvcmos output enable/disable input . see ta ble 2 . 31 pll_en i, pu lvcmos pll enable/disable input . see ta ble 2 . 32 ref_sel i, pd lvcmos reference select input . see table 2 . 3, 4, 5, 6 sel(a:d) i, pd lvcmos frequency select input, bank (a:d) . see ta ble 2 . 27 vddqb supply vdd 2.5v or 3.3v power supply for bank b output clock [2,3] 23 vddqc supply vdd 2.5v or 3.3v power supply for bank c output clocks [2,3] 15, 19 vddqd supply vdd 2.5v or 3.3v power supply for bank d output clocks [2,3] 1 avdd supply vdd 2.5v or 3.3v power supply for pll [2,3] 11 vdd supply vdd 2.5v or 3.3v power supply for core, inputs, and bank a output clock [2,3] 7 avss supply ground analog ground 13, 17, 21, 25, 29 vss supply ground common ground table 1. frequency table fb_sel feedback divider vco input frequency range (avdd = 3.3v) input frequency range (avdd = 2.5v) 0 32 input clock * 32 6.25 mhz to 15.625 mhz 6.25 mhz to 11.875 mhz 1 16 input clock * 16 12.5 mhz to 31.25 mhz 12.5 mhz to 23.75 mhz table 2. function table control default 0 1 ref_sel 0 xtal tclk pll_en 1 bypass mode, pll disabled. the input clock connects to the output dividers pll enabled. the vco output connects to the output dividers oe# 0 outputs enabled outputs disabled (three-state) fb_sel 0 feedback divider 32 feedback divider 16 sela 0 2 (bank a) 4 (bank a ) selb 0 4 (bank b) 8 (bank b) selc 0 4 (bank c ) 8 (bank c) seld 0 4 (bank d) 8 (bank d) notes: 1. pu = internal pull-up, pd = internal pull-down. 2. a 0.1 f bypass capacitor should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead i nductance of the traces. 3. avdd and vdd pins must be connected to a power supply level that is at least equal or higher than that of vddqb, vddqc, and v ddqd output power supply pins. [+] feedback
cy29350 document #: 38-07474 rev. *a page 3 of 7 absolute maximum conditions parameter description condition min. max. unit v dd dc supply voltage ?0.3 5.5 v v dd dc operating voltage functional 2.375 3.465 v v in dc input voltage relative to v ss ?0.3 v dd + 0.3 v v out dc output voltage relative to v ss ?0.3 v dd + 0.3 v v tt output termination voltage v dd 2v lu latch up immunity functional 200 ma r ps power supply ripple ripple frequency < 100 khz 150 mvp-p t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional ?40 +85 c t j temperature, junction functional +150 c ? jc dissipation, junction to case functional 42 c/w ? ja dissipation, junction to ambient functional 105 c/w esd h esd protection (human body model) 2000 volts fit failure in time manufacturing test 10 ppm dc electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.7 v v ih input voltage, high lvcmos 1.7 ? v dd +0.3 v v ol output voltage, low [4] i ol = 15ma ? ? 0.6 v v oh output voltage, high [4] i oh = ?15ma 1.8 ? ? v i il input current, low [5] v il = v ss ? ? ?100 a i ih input current, high [5] v il = v dd ??100 a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 7 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 180 ? ma outputs loaded @ 200 mhz ? 210 ? c in input pin capacitance ? 4 ? pf z out output impedance 14 18 22 ? dc electrical specifications (v dd = 3.3v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.8 v v ih input voltage, high lvcmos 2.0 ? v dd +0.3 v v ol output voltage, low [4] i ol = 24 ma ? ? 0.55 v i ol = 12 ma ? ? 0.30 v oh output voltage, high [4] i oh = ?24 ma 2.4 ? ? v i il input current, low [5] v il = v ss ?? ? ?100 a i ih input current, high [5] v il = v dd ??100 a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 7 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 270 ? ma outputs loaded @ 200 mhz ? 300 ? c in input pin capacitance ? 4 ? pf z out output impedance 12 15 18 ? notes: 4. driving one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, each output drives up to two 50 ? series terminated transmission lines. 5. inputs have pull-up or pull-down resistors that affect the input current. [+] feedback
cy29350 document #: 38-07474 rev. *a page 4 of 7 ac electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) [6] parameter description condition min. typ. max. unit f vco vco frequency 200 ? 380 mhz f in input frequency 16 feedback 12.5 ? 23.75 mhz 32 feedback 6.25 ? 11.87 bypass mode (pll_en = 0) 0 ? 200 f xtal crystal oscillator frequency 10 ? 23.75 mhz f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.7v to 1.7v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 190 mhz 4 output 50 ? 95 8 output 25 ? 47.5 dc output duty cycle f max < 100 mhz 47.5 ? 52.5 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0 .6v to 1.8v 0.1 ? 1.0 ns t sk(o) output-to-output skew ? ? 150 ps t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (-3db) 16 feedback ? 0.7 - 0.9 ? mhz 32 feedback ? 0.6 - 0.8 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 250 t jit(per) period jitter same frequency ? ? 100 ps multiple frequencies ? ? 175 t lock maximum pll lock time ? ? 1 ms ac electrical specifications (v dd = 3.3v 5%, t a = ?40c to +85c) [6] parameter description condition min. typ. max. unit f vco vco frequency 200 ? 500 mhz f in input frequency 16 feedback 12.5 ? 31.25 mhz 32 feedback 6.25 ? 15.625 bypass mode (pll_en = 0) 0 ? 200 f xtal crystal oscillator frequency 10 ? 25 mhz f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.8v to 2.0v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 200 mhz 4 output 50 ? 125 8 output 25 ? 62.5 dc output duty cycle f max < 100 mhz 47.5 ? 52.5 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0.8v to 2.4v 0.1 ? 1.0 ns t sk(o) output-to-output skew banks at same voltage ? ? 150 ps tsk(b) bank-to-bank skew banks at different voltages ? ? 350 ps t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns note: 6. ac characteristics apply for parallel output termination of 50 ? to v tt . parameters are guaranteed by characterization and are not 100% tested. [+] feedback
cy29350 document #: 38-07474 rev. *a page 5 of 7 bw pll closed loop bandwidth (?3db) 16 feedback ? 0.7 ? 0.9 ? mhz 32 feedback ? 0.6 ? 0.8 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 250 t jit(per) period jitter same frequency ? ? 100 ps multiple frequencies ? ? 150 t lock maximum pll lock time ? ? 1 ms ac electrical specifications (v dd = 3.3v 5%, t a = ?40c to +85c)(continued) [6] parameter description condition min. typ. max. unit pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm figure 1. ac test reference for v dd = 3.3v / 2.5v vdd gnd vdd/2 t p t0 dc = tp / t0 x 100% figure 2. output duty cycle (dc) t sk(o) vdd gnd vdd/2 vdd gnd vdd/2 figure 3. output-to- output skew , t sk(o) table 3. suggested oscillator crystal parameters characteristic symbol con ditions min typ max units frequency tolerance t c ? ? 100 ppm frequency temperature stability t s (t a ?10 +60c) ? ? 00 ppm aging t a first three years @ 25c ? ? 5 ppm/yr load capacitance c l crystal?s rated load ? 20 ? pf effective series resistance r esr ?4080 ? ordering information part number package type product flow CY29350AI 32-pin tqfp industrial, ?40 c to +85 c CY29350AIt 32-pin tqfp ? tape and reel industrial, ?40 c to 85 c [+] feedback
cy29350 document #: 38-07474 rev. *a page 6 of 7 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimension spread aware is a trademark of cypress semiconductor. all product and company na mes mentioned in this document are the trademarks of their respective holders. 32-lead thin plastic quad flatpack 7 x 7 x 1.0 mm a32 51-85063-*b [+] feedback
cy29350 document #: 38-07474 rev. *a page 7 of 7 document history page document title:cy29350 2.5v or 3.3v , 200-mhz, 9-output clock driver document number: 38-07474 rev. ecn no. issue date orig. of change description of change ** 128104 07/07/03 rgl new data sheet *a 245393 see ecn rgl re-worded select function descriptions in table 2. [+] feedback
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